Digital-analog converter circuit

ABSTRACT

A digital-analog converter circuit wherein in a pulse interval of input pulses a first capacitor is charged by a power source through a diode, and upon the application of an input pulse the electric charge stored in the said first capacitor is discharged through a grounded-base transistor and simultaneously a second capacitor is charged by the collector current of the said second capacitor is discharged through a resistor in the next pulse interval of the said input pulses.

United States Patent Okamoto et al.

DIGITAL-ANALOG CONVERTER CIRCUIT Atutoshl Oltamoto, Toyohashi; Shunji Oltumura, Kariya, both of Japan Nlppondenso Kabushlltl Kalsha, Aichiken, Japan Filed: May 6, 1970 Appl. No.: 35,126

Inventors:

Assignee:

Forelgn Appllcatlon Priority Data May 9, 1969 Nov. 19, 1969 Japan ....44/93279 US. Cl. ..307/227, 307/261 Int. Cl. ..H03lt 7/00 Field of Search ..307/228, 225, 261, 227,246; 328/186, 184

Japan .L ..44/ 34664 [451 Apr. 4, 1972 [56] References Cited UNITED STATES PATENTS 3,207,923 9/1965 Prager ..328/ 186 X Primary Examiner-Donald D. Forrer Assistant Examiner-B. P; Davis Attorney-Cushman, Darby & Cushman [5 7] ABSTRACT the said second capacitor is discharged through a resistor in the next pulse interval of the said input pulses.

2 Claims, 10 Drawing Figures 1 DIGITAL-ANALOG CONVERTER CIRCUIT FIELD OF THE INVENTION The present invention relates to a digital-analog converter circuit (hereinafter referred to simply as a DA converter circuit) which is adapted to produce a DC output voltage directly proportional to the number or the frequency of input pulses, and the present invention aims at providing a cheap D-A converter circuit of simple construction which produces a DC output voltage which is exactly and directly proportional to the number or the frequency of input pulses and is stable against variation in the ambient temperature.

BRIEF DESCRIPTION OF THE DRAWING FIG. la is a connection diagram showing a conventional well-known accumulating type D-A converter circuit.

FIG. 1b is a connection diagram showing a conventional well-known frequency-voltage conversion type D-A converter circuit.

FIG. 2a shows a characteristic curve of the conventional circuit shown in FIG. la.

FIG. 2b shows a characteristic curve of the conventional circuit shown in FIG. lb.

FIG. 3a is a connection diagram showing an accumulating type D-A converter circuit which is a first embodiment of the present invention.

FIG. 3b is a connection diagram showing a frequency-voltage conversion type D-A converter circuit which is a second embodiment of the present invention.

FIG. 4a shows a characteristic curve of the circuit embodying the present invention shown in FIG. 3a.

FIG. 4b shows a characteristic curve of the circuit embodying the present invention shown in FIG. 3b.

FIG. 5a is a connection diagram showing another accumulating type D-A converter circuit which is a third embodiment of the present invention and a modification of the said first embodiment shown in FIG. 30.

FIG. 5b is a connection diagram showing another frequency-voltage conversion type D-A converter circuit which is a fourth embodiment of the present invention and a modification of the said second embodiment shown in FIG. 3b.

In the above-mentioned drawings, identical reference numerals designate the same or equivalent components.

DESCRIPTION OF THE PRIOR ART An example of a conventional well-known D-A converter circuit of this kind is shown in FIG. la.

In FIG. la, numerals l and Z'designate a first and second capacitors, 3 and 8 diodes, 5 and 5' input terminals, 6 and 6 output terminals. The input terminal 5' and the output terminal 6 are held at ground potential.

The operation of the circuit of the above-mentioned construction will be described hereunder. Now, suppose that both the first capacitor 1 and the second capacitor 2 initially store no electric charge therein. Under that condition, when a negative pulse having a peak voltage value of E (volt) is applied between the input terminals 5 and 5', the diode 3 becomes conductive, the diode 8 becomes noriconductive and the first capacitor 1 is charged through the diode 3 to have the polarity as shown in FIG. la. If the charging time constant ismade sufficiently small as compared with the width of the input pulse, the terminal voltage of the said'first capacitor 1 becomes E (volt). Then, when the input pulse vanishes and the voltage between the input terminals 5 and 5' returns to zero (volt), the diode 3 becomes nonconductive, the diode 8 becomes conductive, and the second capacitor 2 is charged by the charge stored in the first capacitor 1, thereby producing a DC voltage having a value of V,=( C,/C,+C,)-E (volt) across the second capacitor 2, consequently between the output terminals 6 and 6, where c and C are respectively capacitances (farad) of the first capacitor 1 and the second capacitor 2. And in describing the operations of the second and subsequent input pulses, taking into consideration that the second capacitor 2 has already been charged by the preceding input pulses, the voltage across the second capacitor 2, i.e., the output voltage V (volt) produced between the output terminals 6 and 6' is given by:

VAFE'I 2/ I 2) (I As apparently seen from the above expression, the output voltage V is not directly proportional to the number N of the input pulses, whereas its increments -become smaller as the number N of theinput pulses becomes larger. The relation of the above expression (1) is shown in FIG. 2a; Suppose now, for example, that an accumulating type D-A converter circuit shown in FIG. la is followed by and connected to a voltage comparator circuit and a discharge circuit (a reset circuit) and that the set voltage v (volt) of the said voltage comparator circuit is chosen within the range of:

. V V V 2 where V, and V,, are the respective output voltages produced between the output terminals 6 and 6 when five and six input pulses are applied to the input terminals. In this case, when the sixth input pulse is applied to the input terminals, the output voltage Vy of the accumulating type D-A converter circuit exceeds the set voltage V of the voltage comparator circuit and the voltage comparator circuit produces one output pulse, at the same time the electric charge stored in the second capacitor 2 is discharged through the discharge circuit to thereby reset the output voltage Vy of the accumulating type D-A converter circuit to zero (volt). Thus, if the relation of the above expression (2) is detennined, the combination of the accumulating type D-A converter circuit, the voltage comparator circuit and the discharge circuit operates as a hexonal counter circuit.

However, in the aforesaid conventional accumulating type D-A converter circuit, the output voltage v produced between the output terminals 6 and 6 is not directly proportional to the number of the input pulses, whereas the output voltage increment becomes smaller as the number of the input pulses becomes larger. Therefore, even a slight variation in the peak voltage value of an input pulse or the set voltage V of the voltage comparator circuit tends to cause an error.

As a method for eliminating the above-mentioned error, it is well-known that the capacitances of the first capacitor 1 and the second capacitor 2 should be chosen to satisfy the relation C C whereby the following expression holds:

It shows that the output voltage V,,, is directly proportional to the number N of the input pulses. However, as the relation C C is well satisfied, any increment of the output voltage V for each one input pulse becomes remarkably small, hence it will be necessary to increase the peak voltage value E of an input pulse thereby introducing a new problem of being impracticable. Hence, a second measure is generally taken to leave the output voltage V in the small value state and amplify it to have a desired voltage level by means of a DC amplifier. However, this method has such drawbacks that an expensive DC amplifier must be employed and that in an ordinary DC amplifier the amplification degree tends to be varied due to variations in the ambient temperature and a variation with time (drift) etc. also cannot be ignored thereby causing a variation in the output voltage.

Now, another example of a conventional well-known D-A converter circuit of this kind is shown in FIG. 1b.

Similarly to the case of FIG. la, a negative pulse having a peak voltage value of E (volt) which is initially applied between the input terminals 5 and 5 causes a DC output voltage having a value of V1=(C|/C1+C2)'E (volt) to appear across the second capacitor 2, consequently between the output terminals 6 and 6. In this case, however, at the same time when another negative pulse is again applied between the input tenninals 5 and 5' to make the diode 3 conductive, the diode 8 noriconductive and the first capacitor 1 be charged to have a voltage of E( volt), the electric charge of the capacitor 2 is discharged through a resistor 9. If the discharge starting time is taken at i=0, the terminal voltage V of the second capacitor 2 is expressed by the following expression by employing an exponential function exp:

where t denotes time (second), R the resistance value (ohm) of the resistor 9, V, the terminal voltage (volt) of the first capacitor 1.

Now, if the input pulse frequency 15 represented by f (Hz) and the period by T (second), when the time arrives at r-=T, the input pulse vanishes to thereby make the diode 3 nonconductive, the diode 8 conductive and the second capacitor 2 be charged by the electric charge of the first capacitor 1. Taking into consideration in this case that the second capacitor 2 has been charged to have a voltage of if n is increased to infinite and V, represents the limit value of V,, considering the conditions K l, 0 e l, the following will result:

lim (K e)'==0 n 1 hence V,=lim V,

n x =K,.E/l-K,-e (5) The voltage V, which is obtained by the above expression (5) represents the output voltage (volt) produced between the output terminals 6 and 6 when the input pulse frequency f(Hz), is in a steady state.

Now, as is known,

Hereupon, if it is assumed that the relation T/C R l holds, i.e., the pulse interval of the input pulses is sufficiently smaller than the time constant C R, which means that the input pulse frequency f is sufficiently high, the third and following terms on the right side of the above expression (6) may be neglected, and the above expression (5) may be represented as:

As clarified by the above expression (7) and as shown in FIG. 2b, the output voltage V, (volt) is not directly proportional to the input pulse frequency f (Hz), and the increments of the output voltage V,(volt) become smaller as the input pulse frequency f (Hz) goes higher.

in a conventional method, in order to solve such a problem, the capacitances of the first capacitor 1 and the second capacitor 2 are chosen so as the satisfy the condition C, C,.

in this case,

Then the above expression (7) may be represented as:

I'R'f'E 8 which shows that the output voltage V, (volt) is directly proportional to the input pulse frequency f (Hz). However, the better the condition C, C, is satisfied UNDER A given value of C the smaller will become the-increments of the output voltage V, for each one input pulse, hence'there arises as problem similar to that described in connection with FIGS. -la and 2a that the peak voltage value E of the input pulses must be made larger thereby bringing about practical difficulties. That is, a second measure should be generally taken to amplify the original small output voltage V, to have a desired voltage level by means of a DC amplifier which cannot be free from the various defects as already described.

SUMMARY OF THE INVENTION The object of the present invention is to provide a D-A converter circuit wherein a grounded-base transistor circuit is employed in place of the diode in order to remove the abovedescirbed defects so that a DC output voltage produced by a digital-analog conversion, which is directly proportional to the number or the frequency of input pulses and large enough to require no amplification, and which is further not influenced by the ambient temperature, may be obtained.

According to the present invention, inthe absence of an input pulse a first capacitor is charged by a power source through a diode, and upon the application of input pulses the electric charge of the said first capacitor is discharged through a grounded-base transistor and simultaneously a second capacitor is charged by the collector current of the said transistor, hence the terminal voltage of the said second capacitor goes up in direct proportion to the number of the input pulses so that a DC output voltage directly proportional to the number of the input pulses can be obtained between both terminals of the said second capacitor. Also, when the ratio between the capacitances of the above two capacitors is suitably chosen, it is possible to raise the maximum valueof the DC output voltage to an extent nearer the power source voltage.

In addition to the above-mentioned feature, if the electric charge stored in the said second capacitor is discharged through a resistor, an average value of the terminal voltage of the saidsecond capacitor goes up in direct proportion to the frequency of the input pulses so that an average output voltage directly proportional to the frequency of the input pulses, i.e., an analog DC voltage produced by converting a digital signal into an analog signal can be obtained between both terminals of the said second capacitor. Further, as it is not necessary to make the ratio between the capacitances of the said two capacitors a large value, by suitably selecting the capacitance value of only the said first capacitor the maximum value of the dc output voltage produced by the digital-analog conversion can be raised to an extent nearer the power source voltage.

As described hereinbefore, the present invention has such excellent advantages that it is not necessary to amplify the DC voltage produced by the digital-analog conversion and so it is possible to dispense with an expensive dc amplifier and to greatly cut down the cost, further that a variation in the analog DC voltage due to a variation in the ambient temperature can be avoided, and in addition, according to the circuit of the present invention, the analog output voltage is proportional to a current amplification factor a of the said grounded-base transistor and the current amplification factor a is dispersed within the range of substantially 0.95-0.995, hence a variation in the analog DC voltage can be confined within a very small range even when the said transistor is replaced by another one owing to some fault, etc.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described hereunder with respect to the embodiments shown in the drawings.

In FIG. 3a which shows a first embodiment of the present invention, circuit components indicated by numerals l, 2, 3, 5, 5, 6 and 6' are identical with those shown in FIG. la. The cathode of the diode 3 is connected to one terminal of a first capacitor 1 and the anode thereof is connected to a positive terminal 7 of a power source. Numeral 4 designates a pnp type transistor, whosc'emitter is connected to the junction point of one terminal of the first capacitor 1 and the cathode of the diode 3, whose base is connected to the terminal 7 of the power source, and whose collector is connected to one terminal of a second capacitor 2, thereby forming a groundedbase connection. An input terminal 5 and an output terminal 6' are held at ground potential. 7

Now, the operation of the circuit of the above construction according to the present invention will be described hereunder. At the beginning when the capacitor 2 holds no electric charge, no input signal is applied, and the voltage between input terminals 5 and 5' is zero volt, the first capacitor l of the capacitance C (farad) is charged by the power source through the diode 3 to have a voltage thereacross reaching the power source voltage E (volt) and the polarity as shown in FIG. 3a. In this state, if a positive pulse having a peak voltage value of E (volt) is applied between the input terminals 5 and 5', the diode 3 becomes nonconductive and the first capacitor 1 is discharged through the transistor 4 until the potential difference thereacross becomes 5 -15 (volt). If the charging and discharging time constants of the first capacitor 1 are made sufficiently small, the amount of electric charge which is discharged for each one input pulse is given by C -E (coulomb). As the transistor 4 is connected in a groundedbase configuration, the amount of electric charge which is stored in the second capacitor 2 of capacitance C (farad) by a collector current flowing through the transistor 4 is the product of the aforesaid amount of discharged electric charge and the current amplification factor a of the grounded-base transistor 4. Consequently, a voltage produced across the second capacitor 2 for each one input pulse is given by:

I i/ D (volt) Then, when N input pulses are applied between the input terminals 5 and 5, an output voltage V produced across the second capacitor 2, i.e., between the output terminals 6 and 6' is represented by:

As is apparent from the above expression (9), the output voltage V is directly proportional to the number N of the input pulses. The relation of the above expression (9) is shown in FIG. 4a. In FIG. 4a, the horizontal axis is scaled with the pulse number and the vertical axis is sealed with the output voltage, and symbols E and E on the vertical axis denote the power source voltage and the peak voltage value of an input pulse respectively. In this case, as there is no need tosatisfy the condition C, C by suitably determining the ratio between C, and C, in accordance with the value of the number N of the input pulses, it is possible to make the maximum value of the output voltage V reach nearer the power source voltage E While a PNP type transistor 4 has been employed in the above first embodiment, a NPN type transistor 4' may be employed instead thereof as in the third embodiment shown in FIG. 5a. And, in the same way as the above case of employing a PNP type transistor 4, a DC output voltage which is directly proportional to the number of input pulses applied between the input terminals 5 and 5' can be produced between the output terminals 6 and 6'.

Now, in FIG. 3b which shows a second embodiment of the present invention, circuit components indicated by numerals l, 2, 3, 5, 5, 6, 6' and 9 are identical with those shown in FIG. lb. The circuit shown in FIG. 3b has such a construction that a resistor 9 has been connected in parallel with the capacitor 2 in FIG. 3a showing a first embodiment of the present invention.

As explanation will b made of the second embodiment in respect of the difference thereof from the first embodiment shown in FIG. 3a.

When an input pulse disappears after it has been applied to the input terminals, the electric charge stored in the second capacitor 2 is discharged through the resistor 9. If a voltage drop which takes place during one pulse interval T of the input pulses is designated as AV and the peak voltage value of an output pulse as V,,, their relation is given by:

Further, as a voltage rise is equal to a voltage drop in the steady state, the following results:

' The above expression (10) gives the peak value V, of the out- Thus, the expression which is equivalent to the previous expression (8) can be obtained. However, as apparently seen from the above expression (ll), the average output voltage 7, is exactly and directly proportional to the frequency f of input pulses. The relation of the above expression (1 l) is shown in FIG. 4b. In FIG. 4b, the horizontal axis is scaled with he frequency f (Hz) of the input pulses and the vertical axis is sealed with the average output voltage 7, (volt), and symbols e and E on the vertical axis denote the power source voltage (volt) and the peak voltage value (volt) of an input pulse respectively. in the same way as the first embodiment shown in H6. 30, there is no need to satisfy the condition of c, C by suitably choosing the capacitance C of the first capacitor 1, it is possible to make the maximum value of the average output voltage V, reach nearer the power source voltage E and independently of the peak voltage value E of an input pulse.

While a PNP type transistor 4 has been employed in the above second embodiment, a npn type transistor 4' may be employed instead thereof as in the fourth embodiment shown in FIG. 5b. And, in the same way as the above case of employing a PNP type transistor 4, an average output voltage which is exactly and directly proportional to the frequency of the input pulses applied between the input terminals 5 and 5 can be produced between the output terminals 6 and 6.

We'claim:

l. A digital-analog converter circuit for converting a train of input digital pulses to an analog output proportional to the number of input pulses, said circuit comprising:

an input terminal means for receiving said train of input digital pulses,

a source terminal for connection to a DC power source,

a series circuit of a first capacitor and a diode connected between said input terminal and said source terminal to result in continuous charging of said first capacitor by said DC power source in the absence of an input pulse,

output terminals having a second capacitor connected thereacross,

a transistor with its collector-emitter circuit being connected in series between one of said output terminals and the junction of said first capacitor and diode,

a base electrode of said transistor being connected to said source terminal whereby a predetermined charging current flows to said second capacitor each time an input pulse is applied to said input terminal.

2. A digital-analog converter circuit as in claim 1 further comprising a resistor means connected across said second capacitor for producing a continuous rather than stepwise output waveform, which continuous waveform is substantially linearly proportional to the input pulse frequency.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 652J 2i87 Dated April L, 1972 Inventor(s) OKAMOTO, Atutoshi and OKUMURA, Shunji It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

In the heading under Foreign Applice tion Priority Date, read Ma 97 969 Japan L L/3466 l as --May 6, 1969 Ja pan, 4 1 66 i.

Signed and sealed this 5th'day of September 1972.

(SEAL) Attest:

ROBERT GOTTSCHALK EDWARD M.FLETCHER,JR. Attesting Officer Commissioner of Patents USCOMM'DC 60376-P69 U45 GOVERNMENT PRINTING OFFICE 199 0-366-33 FORM PO-OSO (10-69) 

1. A digital-analog converter circuit for converting a train of input digital pulses to an analog output proportional to the number of input pulses, said circuit comprising: an input terminal means for receiving said train of input digital pulses, a source terminal for connection to a DC power source, a series circuit of a first capacitor and a diode connected between said input terminal and said source terminal to result in continuous charging of said first capacitor by said DC power source in the absence of an input pulse, output terminals having a second capacitor connected thereacross, a transistor with its collector-emitter circuit being connected in series between one of said output terminals and the junction of said first capacitor and diode, a base electrode of said transistor being connected to said source terminal whereby a predetermined charging current flows to said second capacitor each time an input pulse is applied to said input terminal.
 2. A digital-analog converter circuit as in claim 1 further comprising a resistor means connected across said second capacitor for producing a continuous rather than stepwise output waveform, which continuous waveform is substantially linearly proportional to the input pulse frequency. 